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INTEGRATED CIRCUITS
DATA SHEET
TDA8752 Triple high speed Analog-to-Digital Converter (ADC)
Product specification Supersedes data of 1998 Aug 11 File under Integrated Circuits, IC02 1999 Mar 09
Philips Semiconductors
Product specification
Triple high speed Analog-to-Digital Converter (ADC)
FEATURES * Triple 8-bit ADC * Sampling rate up to 100 MHz * IC controllable via a serial interface, which can be either I2C-bus or 3-wire, selected via a TTL input pin * IC analog voltage input from 0.4 to 1.2 V (p-p) to produce full-scale ADC input of 1 V (p-p) * 3 clamps for programming a clamping code between -63.5 and +64 in steps of 12LSB * 3 controllable amplifiers: gain controlled via the serial interface to produce a full scale resolution of 12LSB peak-to-peak * Amplifier bandwidth of 250 MHz * Low gain variation with temperature * PLL, controllable via the serial interface to generate the ADC clock, which can be locked to a line frequency from 15 to 280 kHz * Integrated PLL divider * Programmable phase clock adjustment cells * Internal voltage regulators * TTL compatible digital inputs and outputs * Chip enable high-impedance ADC output * Power-down mode * Possibility to use up to four ICs in the same system, using the I2C-bus interface, or more, using the 3-wire serial interface * 1 W power dissipation. APPLICATIONS * R, G and B high speed digitizing * LCD panels drive * LCD projection systems * VGA and higher resolutions * Using two ICs in parallel, higher display resolution can be obtained; 200 MHz pixel frequency. ORDERING INFORMATION TYPE NUMBER TDA8752H/6 TDA8752H/8 PACKAGE NAME DESCRIPTION VERSION SOT317-2 GENERAL DESCRIPTION
TDA8752
The TDA8752 is a triple 8-bit ADC with controllable amplifiers and clamps for the digitizing of large bandwidth RGB signals. The clamp level, the gain and all of the other settings are controlled via a serial interface (either I2C-bus or 3-wire serial bus, selected via a logic input). The IC also includes a PLL that can be locked on the horizontal line frequency and generates the ADC clock. The PLL jitter is minimized for high resolution PC graphics applications. An external clock can also be input to the ADC. It is possible to set the TDA8752 serial bus address between four fixed values, in the event that several TDA8752 ICs are used in a system, using the I2C-bus interface (for example, two ICs used in an odd/even configuration).
SAMPLING FREQUENCY (MHz) 60 100
plastic quad flat package; 100 leads (lead length 1.95 mm); QFP100 body 14 x 20 x 2.8 mm
1999 Mar 09
2
Philips Semiconductors
Product specification
Triple high speed Analog-to-Digital Converter (ADC)
QUICK REFERENCE DATA SYMBOL VCCA VDDD VCCD VCCO VCCA(PLL) VCCO(PLL) ICCA IDDD ICCD ICCO ICCA(PLL) ICCO(PLL) fCLK fref(PLL) fVCO INL PARAMETER analog supply voltage logic supply voltage digital supply voltage output stages supply voltage analog PLL supply voltage output PLL supply voltage analog supply current logic supply current digital supply current output stages supply current analog PLL supply current output PLL supply current maximum clock frequency PLL reference clock frequency VCO output clock frequency DC integral non linearity from analog input to digital output; full-scale; ramp input; fCLK = 100 MHz from analog input to digital output; full-scale; ramp input; fCLK = 100 MHz Vref = 2.5 V with 100 ppm/C maximum -3 dB; Tamb = 25 C TDA8752/6 TDA8752/8 fCLK = 100 MHz; ramp input for I2C-bus and 3-wire for R, G and B channels CONDITIONS for R, G and B channels for I2C-bus and 3-wire MIN. 4.75 4.75 4.75 4.75 4.75 4.75 - - - - - - 60 100 15 12 - TYP. 5.0 5.0 5.0 5.0 5.0 5.0 120 1.0 40 6 28 5 - - - - 0.5
TDA8752
MAX. 5.25 5.25 5.25 5.25 5.25 5.25 - - - - - - - - 280 100 1.5
UNIT V V V V V V mA mA mA mA mA mA MHz MHz kHz MHz LSB
DNL
DC differential non linearity
-
0.5
1.0
LSB
Gamp/T B tset DRPLL Ptot jPLL(rms)
amplifier gain stability as a function of temperature amplifier bandwidth settling time of the ADC block plus AGC PLL divider ratio total power consumption maximum PLL phase jitter (RMS value)
- 250
- - - - 1.0 0.3
200 - 6 4095 - -
ppm/C MHz ns
input signal settling - time < 1 ns; Tamb = 25 C 100 fCLK = 100 MHz; ramp input fref = 66.67 kHz; fCLK = 100 MHz - -
W ns
1999 Mar 09
3
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1999 Mar 09
RAGC RGAINC RIN RDEC Vref GAGC GGAINC GIN GDEC BAGC
BLOCK DIAGRAM
Philips Semiconductors
Triple high speed Analog-to-Digital Converter (ADC)
VCCAR
VCCAB
VCCOR
VCCOB VCCA(PLL) VCCD 59 95
CLP
AGNDG
VSSD
OGNDG AGNDPLL
DGND
VCCAG 11 6 8 12 10 19
VDDD 27 40
VCCOG 79 69
VCCO(PLL) AGNDR
AGNDB 21 29
OGNDR 41 70
OGNDB OGNDPLL 60 48 96 82 86 9 7 RCLP RBOT
99
85
89
13
CLAMP MUX OUTPUTS ADC
71 to 78 R0 to R7 45
3
ROR
RED CHANNEL
14 16 20 18 22 24 28 26 17 15 61 to 68 GCLP GBOT G0 to G7 46 87 25 23 49, 52 to 58 GOR OE BCLP BBOT B0 to B7 BOR
GREEN CHANNEL
4
BGAINC BIN BDEC
BLUE CHANNEL
47
TDO TCK ADD2 ADD1 SEN SCL SDA DIS I2C/3W
36 35 34 33 38 42 39 37 32 1, 5, 30, 31, 43 , 44 50, 51, 100 n.c. SERIAL INTERFACE I2C-BUS OR 3-WIRE I2C-bus; 1-bit (H level) 84 HSYNCI CKADCO CKBO CKAO CKREFO CKEXT INV COAST
TDA8752
83 81 80
REGULATOR PLL 92 91 93 94 90 HSYNC 4 DEC1 2 88 97 CP 98
MGG363
Product specification
CKREF
TDA8752
DEC2 PWDWN
CZ
Fig.1 Block diagram.
Philips Semiconductors
Product specification
Triple high speed Analog-to-Digital Converter (ADC)
TDA8752
CLP
handbook, full pagewidth
RAGC
CLKADC
RCLP VP 150 k MUX 3 k 45 k
CLAMP CONTROL DAC 8 AGC ADC REGISTER I2C-bus; 8 bits (Or) OUTPUTS 8 DAC DR 1 D R 8 7 1 REGISTER COARSE GAIN ADJUST I2C-bus; 7 bits (Cr) SERIAL I2C-BUS RBOT OE
RIN Vref
ROR
VCCAR
8
R0 to R7
5 REGISTER FINE GAIN ADJUST I2C-bus; 5 bits (Fr)
MGG364
HSYNCI RGAINC
Fig.2 Red channel diagram.
1999 Mar 09
5
Philips Semiconductors
Product specification
Triple high speed Analog-to-Digital Converter (ADC)
TDA8752
handbook, full pagewidth
Cz COAST CZ CP
Cp CKEXT INV
I2C-bus; 1 bit (V level) loop filter I2C-bus; 3 bits (Z) VCO 12 to 100 MHz MUX 0/180 CKADCO
CKREF
PHASE FREQUENCY edge selector DETECTOR I2C-bus; 1 bit I2C-bus; 5 bits (edge) (Ip, Up, Do)
I2C-bus; phase selector A 2 bits (VCO) I2C-bus; I2C-bus; 5 bits (Pa) 1 bit (Cka)
CLK ADC CKBO
DIV N (100 to 4095) I2C-bus; 12 bits (Di) phase selector B I2C-bus; 5 bits (Pb) I2C-bus; 1 bit (Ckb)
CKAO
SYNCHRO
CKREFO
MGG370
Fig.3 PLL diagram.
1999 Mar 09
6
Philips Semiconductors
Product specification
Triple high speed Analog-to-Digital Converter (ADC)
PINNING SYMBOL n.c. DEC2 Vref DEC1 n.c. RAGC RBOT RGAINC RCLP RDEC VCCAR RIN AGNDR GAGC GBOT GGAINC GCLP GDEC VCCAG GIN AGNDG BAGC BBOT BGAINC BCLP BDEC VCCAB BIN AGNDB n.c. n.c. I2C/3W ADD1 ADD2 TCK PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 not connected main regulator decoupling input gain stabilizer voltage reference input main regulator decoupling input not connected red channel AGC output red channel ladder decoupling input (BOT) red channel gain capacitor input red channel gain clamp capacitor input red channel gain regulator decoupling input red channel gain analog power supply red channel gain analog input red channel gain analog ground green channel AGC output green channel ladder decoupling input (BOT) green channel gain capacitor input green channel gain clamp capacitor input green channel gain regulator decoupling input green channel gain analog power supply green channel gain analog input green channel gain analog ground blue channel AGC output blue channel ladder decoupling input (BOT) blue channel gain capacitor input blue channel gain clamp capacitor input blue channel gain regulator decoupling input blue channel gain analog power supply blue channel gain analog input blue channel gain analog ground not connected not connected DESCRIPTION
TDA8752
selection input between I2C-bus (active HIGH) and 3-wire serial bus (active LOW) I2C-bus address control input 1 I2C-bus address control input 2 scan test mode (active HIGH)
1999 Mar 09
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Philips Semiconductors
Product specification
Triple high speed Analog-to-Digital Converter (ADC)
SYMBOL TDO DIS SEN SDA VDDD VSSD SCL n.c. n.c. ROR GOR BOR OGNDB B0 n.c. n.c. B1 B2 B3 B4 B5 B6 B7 VCCOB OGNDG G0 G1 G2 G3 G4 G5 G6 G7 VCCOG OGNDR R0 PIN 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 scan test output I2C and 3W disable control input (disable at HIGH level) select enable for 3-wire serial bus input (see Fig.10) I2C/3W serial data input logic I2C/3W digital power supply logic I2C/3W digital ground I2C/3W serial clock input not connected not connected red channel ADC output bit out of range green channel ADC output bit out of range blue channel ADC output bit out of range blue channel ADC output ground blue channel ADC output bit 0 (LSB) not connected not connected blue channel ADC output bit 1 blue channel ADC output bit 2 blue channel ADC output bit 3 blue channel ADC output bit 4 blue channel ADC output bit 5 blue channel ADC output bit 6 blue channel ADC output bit 7 (MSB) blue channel ADC output power supply green channel ADC output ground green channel ADC output bit 0 (LSB) green channel ADC output bit 1 green channel ADC output bit 2 green channel ADC output bit 3 green channel ADC output bit 4 green channel ADC output bit 5 green channel ADC output bit 6 green channel ADC output bit 7 (MSB) green channel ADC output power supply red channel ADC output ground red channel ADC output bit 0 (LSB) DESCRIPTION
TDA8752
1999 Mar 09
8
Philips Semiconductors
Product specification
Triple high speed Analog-to-Digital Converter (ADC)
SYMBOL R1 R2 R3 R4 R5 R6 R7 VCCOR CKREFO CKAO OGNDPLL CKBO CKADCO VCCO(PLL) DGND OE PWDWN CLP HSYNC INV CKEXT COAST CKREF VCCD AGNDPLL CP CZ VCCAPLL n.c. PIN 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 red channel ADC output bit 1 red channel ADC output bit 2 red channel ADC output bit 3 red channel ADC output bit 4 red channel ADC output bit 5 red channel ADC output bit 6 red channel ADC output bit 7 (MSB) red channel ADC output power supply reference output clock resynchronized horizontal pulse PLL clock output 3 (in phase with reference output clock) PLL digital ground PLL clock output 2 PLL clock output 1 (in phase with internal ADC clock) PLL output power supply digital ground output enable not (when OE is HIGH, the outputs are in high-impedance) DESCRIPTION
TDA8752
power-down control input (IC is in power-down mode when this pin is HIGH) clamp pulse input (clamp active HIGH) horizontal synchronization input pulse PLL clock output inverter command input (invert when HIGH) external clock input PLL coast command input PLL reference clock input digital power supply PLL analog ground PLL filter input PLL filter input PLL analog power supply not connected
1999 Mar 09
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Philips Semiconductors
Product specification
Triple high speed Analog-to-Digital Converter (ADC)
TDA8752
85 VCCO(PLL)
99 VCCA(PLL)
84 CKADCO
88 PWDWN
handbook, full pagewidth
82 OGNDPLL
96 AGNDPLL
90 HSYNC
93 COAST
94 CKREF
92 CKEXT
86 DGND
83 CKBO
100 n.c.
n.c. DEC2 Vref DEC1 n.c. RAGC RBOT RGAINC RCLP
1 2 3 4 5 6 7 8 9
81 CKAO 80 79 78 77 76 75 74 73 72 71 70 69 68 67
95 VCCD
89 CLP
91 INV
87 OE
97 CP
98 CZ
CKREFO VCCOR R7 R6 R5 R4 R3 R2 R1 R0 OGNDR VCCOG G7 G6 G5 G4 G3 G2 G1 G0 OGNDG VCCOB B7 B6 B5 B4 B3 B2 B1 n.c.
RDEC 10 VCCAR 11 RIN 12 AGNDR 13 GAGC 14 GBOT 15 GGAINC 16 GCLP 17 GDEC 18 VCCAG 19 GIN 20 AGNDG 21 BAGC 22 BBOT 23 BGAINC 24 BCLP 25 BDEC 26 VCCAB 27 BIN 28 AGNDB 29 n.c. 30 n.c. 31 I2C/3W 32 ADD1 33 ADD2 34 TCK 35 TDO 36 DIS 37 SEN 38 SDA 39 VDDD 40 VSSD 41 SCL 42 n.c. 43 n.c. 44 ROR 45 GOR 46 BOR 47 OGNDB 48 B0 49 n.c. 50
TDA8752
66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
MGG362
Fig.4 Pin configuration.
1999 Mar 09
10
Philips Semiconductors
Product specification
Triple high speed Analog-to-Digital Converter (ADC)
FUNCTIONAL DESCRIPTION This triple high-speed 8-bit ADC is designed to convert RGB signals, from a PC or work station, into data used by a LCD driver (pixel clock up to 200 MHz, using 2 ICs). IC analog video inputs The video inputs are internally DC polarized. These inputs are AC coupled externally. Clamps Three independent parallel clamping circuits are used to clamp the video input signals on the black level and to control the brightness level. The clamping code is programmable between code -63.5 and +64 in steps of 1 LSB. The programming of the clamp value is achieved 2 via an 8-bit DAC. Each clamp must be able to correct an offset from 0.1 V to 10 mV within 300 ns, and correct the total offset in 10 lines. The clamps are controlled by an external TTL positive going pulse (pin CLP). The drop of the video signal is <1 LSB. Normally, the circuit operates with a 0 code clamp, corresponding to the 0 ADC code. This clamp code can be changed from -63.5 to +64 as represented in Fig.7, in steps of 12LSB. The digitized video signal is always between code 0 and code 255 of the ADC. Variable gain amplifier Three independent variable gain amplifiers are used to provide, to each channel, a full-scale input range signal to the 8-bit ADC. The gain adjustment range is designed so that, for an input range varying from 0.4 to 1.2 V (p-p), the output signal corresponds to the ADC full-scale input of 1 V (p-p). To ensure that the gain does not vary over the whole operating temperature range, an external reference of +2.5 V DC, (Vref with a 100 ppm/C maximum variation) supplied externally, is used to calibrate the gain at the beginning of each video line before the clamp pulse using the following principle. A differential of 0.156 V (p-p) (116Vref) reference signal is generated internally from the reference voltage (Vref). During the synchronization part of the video line, the multiplexer, controlled by the TTL synchronization signal (HSYNCI, coming from HSYNC; see Fig.1) with a width equal to one of the video synchronization signals (e.g. signal coming from a synchronization separator), is switched between the two amplifiers.
TDA8752
The output of the multiplexer is either the normal video signal or the 0.156 V reference signal (during HSYNC). The corresponding ADC outputs are then compared to a pre-set value loaded in a register. Depending on the result of the comparison, the gain of the variable gain amplifiers is adjusted (coarse gain control; see Figs 2 and 8). The three 7-bit registers receive data via a serial interface to enable the gain to be programmed. The pre-set value loaded in the 7-bit register is chosen between approximately 67 codes to ensure the full-scale input range (see Fig.8). A contrast control can be achieved using these registers. In this case care should be taken to stay within the allowed code range (32 to 99). A fine correction using three 5-bit DACs, also controlled via the serial interface, is used to finely tune the gain of the three channels (fine gain control; see Figs 2 and 9) and to compensate the channel-to-channel gain mismatch. With a full scale ADC input, the resolution of the fine register corresponds to 12LSB peak-to-peak variation. To use these gain controls correctly, it is recommended to fix the coarse gain (to have a full-scale ADC input signal) to within 4LSB and then adjust it with the fine gain. The gain is adjusted during HSYNC. During this time the output signal is not related to the amplified input signal. The outputs, when the coarse gain system is stable, is related to the programmed coarse code (see Fig.8). ADCs The ADCs are 8-bit with a maximum clock frequency of 100 Msps. The ADCs input range is 1 V (p-p) full-scale. One out of range bit exists per channel (ROR, GOR and BOR). It will be at logic 1 when the signal is out of range of the full scale of the ADCs. Pipeline delay in the ADCs is 1 clock cycle from sampling to data output. The ADCs reference ladders regulators are integrated. ADC outputs ADC outputs are straight binary. An output enable pin (OE; active LOW) enables the output status between active and high-impedance (OE = HIGH) to be switched; it is recommended to load the outputs with a 10 pF capacitive load. The timing must be checked very carefully if the capacitive load is more than 10 pF.
1999 Mar 09
11
Philips Semiconductors
Product specification
Triple high speed Analog-to-Digital Converter (ADC)
Phase-locked loop The ADCs are clocked either by an internal PLL locked to the CKREF clock, (all of the PLL is on-chip except the loop filter capacitance) or an external clock, CKEXT. Selection is performed via the serial interface bus. The reference clock (CKREF) range is between 15 and 280 kHz. Consequently, the VCO minimum frequency is 12 MHz and the maximum frequency 100 MHz for the TDA8752/8 and 60 MHz for the TDA8752/6. The gain of the VCO part can be controlled via the serial interface, depending on the frequency range to which the PLL is locked. To increase the bandwidth of the PLL, the charge pump current, controlled by the serial interface, must also be increased. The relationship between the frequency and the current is given by the following equation: KO IP 1 f n = ------ ---------------------------------2 ( C z + C P ) N Where: fn = the natural PLL frequency KO = the VCO gain N = the division number Cz and CP = capacitors of the PLL filter. The other PLL equation is as follows: 1 fn 1 f z = ------------------------------ and = -- x --- -2 fz 2 x R x C z Where: fz = loop filter zero frequency R = the chosen resistance for the filter = the damping factor.
TDA8752
Different resistances for the filter can be programmed via the serial interface. To have better performances, the PLL parameters should be chosen so that: fn/fref 0.05 1.5. It is possible to control (independently) the phase of the ADC clock and the phase of an additional clock output (which could be used to drive a second TDA8752). For this, two serial interface-controlled digital phase-shift controllers are included (controlled by 5-bit registers, phase shift controller steps are 11.25 each on the whole PLL frequency range). CKREF is resynchronized, by the synchro block, on the CKAO clock. The output is CKREFO (LOW during 8 clock periods). CKAO is the clock at the output of the phase selector A. This clock can be used as the clocks for CKBO and CKADCO. The timing is given in Fig.5.
andbook, full pagewidth
CKREF
CKAO tCKAO CKREFO tCKREFO
MBK773
t phase selector tCKAO = tCLK(buffer) + tphase selector (tCLK(buffer) = 10 ns and tphase selector = ------------------------------ x TCLK(pixel)). 2 tCKREFO = either tCKAO if phase A 01000 or tCKAO + TCLK(pixel) if phase A <01000.
Fig.5 Timing.
1999 Mar 09
12
Philips Semiconductors
Product specification
Triple high speed Analog-to-Digital Converter (ADC)
The COAST pin is used to disconnect the PLL phase frequency detector during the frame flyback or the unavailability of the CKREF signal. This signal can normally be derived from the VSYNC signal. The clock output is able to drive an external 10 pF load (for the on-chip ADCs). The PLL can be used in three different methods: 1. The IC can be used as stand-alone with a sampling frequency of up to 100 MHz for the TDA8752/8 and up to 60 MHz for the TDA8752/6. 2. When an RGB signal is at a pixel frequency exceeding 100 to 200 MHz, it is possible to follow one of the two possibilities given below; a) Using one TDA8752; the sampling rate can be reduced by a factor of two, by sampling the even pixels in the even frame and the odd pixels in the odd frame. The INV pin is used to toggle between frames.
TDA8752
b) Using two TDA8752s the PLL of the master TDA8752 is used to drive both ADC clocks. The PLL of the slave TDA8752 is disconnected and the CKBO of the master TDA8752 is connected to pin CKEXT of both TDA8752. The master TDA8752 is used to sample the even pixels and the slave TDA8752 for odd pixels, using a 180 phase shift between the clocks (CKADCO pins). The master chip has its INV pin LOW while the slave chip has its INV pin HIGH, which guarantees the 180 shift ADC clock drive. It is then necessary to adjust phase B of the master chip. Special care should be taken with the quality of the input signal (input setting time). If CKREFO output signal at the master chip is needed, it is possible to use one of the two phase A values in order to avoid set-up and hold problems in the SYNCHRO function; e.g. PHASEA = 100000 and PHASEA = 111111.
1999 Mar 09
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Philips Semiconductors
Product specification
Triple high speed Analog-to-Digital Converter (ADC)
TDA8752
handbook, full pagewidth
COAST 12 to 100 MHz
CKEXT
INV
MUX phase selector A I2C-bus; I2C-bus; 5 bits (Pa) 1 bit (Cka) (Cka = 1) CKREF
0/180
CKADCO
CLK ADC CKBO
PLL
phase selector B I2C-bus; 5 bits (Pb)
I2C-bus; 1 bit (Ckb) (Ckb = 1) CKAO
Master TDA8752 (even pixels)
SYNCHRO
CKREFO
COAST 12 to 100 MHz
CKEXT
5V INV
CKADCO MUX phase selector A I2C-bus; I2C-bus; 5 bits (Pa) 1 bit (Cka) (Cka = 1) CKREF 0/180
CLK ADC CKBO
PLL
phase selector B I2C-bus; 5 bits (Pb)
I2C-bus; 1 bit (Ckb) (Ckb = 0) CKAO
Slave TDA8752 (odd pixels)
SYNCHRO
CKREFO
MBK772
Slave at 180 phase shift with respect to pin CKADCO of the master TDA8752.
Fig.6 Dual TDA8752 solution for pixel clock rate with a single phase adjustment (100 to 200 MHz).
1999 Mar 09
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Philips Semiconductors
Product specification
Triple high speed Analog-to-Digital Converter (ADC)
I2C-bus and 3-wire serial bus interface
TDA8752
The I2C-bus and 3-wire serial buses control the status of the different control DACs and registers. Control pin DIS enables or disables the full serial interface function (disable at HIGH level). Four ICs can be used in the same system and programmed by the same bus. Therefore, two pins (ADD1 and ADD2) are available to set each address respectively, for use with the I2C-bus interface. All programming is described in Chapter "I2C-bus and 3-wire interfaces".
handbook, full pagewidth
255 digitized video signal
code 64 code 0 code -63.5 clamp programming
video signal
CLP
MGG368
Fig.7 Clamp definition.
handbook, full pagewidth
Ncoarse code 127 coarse register value (67 codes) 99
ADC output code
G(max)
G(min)
255 227
32 0
160 128 V 0.2 0.156 = ref 16 0.6 Vi (p-p) 2
MGG366
Fig.8 Coarse gain control.
1999 Mar 09
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Philips Semiconductors
Product specification
Triple high speed Analog-to-Digital Converter (ADC)
TDA8752
handbook, full pagewidth
ADC output code 255 G(max) 227 coarse register value (67 codes) GNCOARSE G(min)
NCOARSE 160
128 NFINE = 0 NFINE = 31 Vref
MGG367
Fig.9 Fine gain correction for a coarse gain GNCOARSE.
1999 Mar 09
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Triple high speed Analog-to-Digital Converter (ADC)
Register definitions The configuration of the different registers is as follows: Table 1 I2C-bus and 3-wire registers SUB-ADDRESS A7 - X X X X X X X X X X X X X X A6 - X X X X X X X X X X X X X X A5 - X X X X X X X X X X X X X X A4 - X X X X X X X X X X X X X X A3 - 0 0 0 0 0 0 0 0 1 1 1 1 1 1 A2 - 0 0 0 0 1 1 1 1 0 0 0 0 1 1 A1 - 0 0 1 1 0 0 1 1 0 0 1 1 0 0 A0 - 0 1 0 1 0 1 0 1 0 1 0 1 0 1 MSB X Or7 X X Og7 X X Ob7 X X V level Z2 Di8 X X X Or6 Cr6 X Og6 Cg6 X Ob6 Cb6 X H level Z1 Di7 Di0 X X Or5 Cr5 X Og5 Cg5 X Ob5 Cb5 X edge Z0 Di6 Cka Ckb Mode Or4 Cr4 Fr4 Og4 Cg4 Fg4 Ob4 Cb4 Fb4 Up Vco1 Di5 Pa4 Pb4 Sa3 Or3 Cr3 Fr3 Og3 Cg3 Fg3 Ob3 Cb3 Fb3 Do Vco0 Di4 Pa3 Pb3 Sa2 Or2 Cr2 Fr2 Og2 Cg2 Fg2 Ob2 Cb2 Fb2 Ip2 Di11 Di3 Pa2 Pb2 Sa1 Or1 Cr1 Fr1 Og1 Cg1 Fg1 Ob1 Cb1 Fb1 Ip1 Di10 Di2 Pa1 Pb1 BIT DEFINITION LSB Sa0 Or0 Cr0 Fr0 Og0 Cg0 Fg0 Ob0 Cb0 Fb0 Ip0 Di9 Di1 Pa0 Pb0 DEFAULT VALUE xxx1 0000 0111 1111 x010 0000 xxx0 0000 0111 1111 x010 0000 xxx0 0000 0111 1111 x010 0000 xxx0 0000 0000 0100 0110 0001 1001 0000 x000 0000 xx00 0000
FUNCTION NAME SUBADDR OFFSETR COARSER FINER OFFSETG COARSEG FINEG OFFSETB COARSEB FINEB CONTROL VCO DIVIDER (LSB) PHASEA PHASEB
All the registers are defined by a sub-address of 8 bits; bit A4 refers to the mode which is used with the I2C-bus interface; bits Sa3 to Sa0 are the subaddresses of each register. The bit mode, used only with the I2C-bus, enables two modes to be programmed: * If Mode = 0, each register is programmed independently by giving its sub-address and its content * If Mode = 1, all the registers are programmed one after the other by giving this initial condition (xxx1 1111) as the sub-address state; thus, the registers are charged following the predefined sequence of 16 bytes (from sub-address 0000 to 1101). Product specification
TDA8752
Philips Semiconductors
Product specification
Triple high speed Analog-to-Digital Converter (ADC)
OFFSET REGISTER This register controls the clamp level for the RGB channels. The relationship between the programming code and the level of the clamp code is given in Table 2. Table 2 Coding CLAMP CODE -63.5 -63 -62.5 0 63.5 64 0 63 or 64 64 ADC OUTPUT underflow Table 3
TDA8752
Gain correspondence (COARSE) GAIN 0.825 2.5 Vi TO BE FULL-SCALE 1.212 0.4
NCOARSE 32 99
PROGRAMMED CODE 0 1 2 127 254 255
The default programmed value is as follows: * NCOARSE = 32 * Gain = 0.825 * Vi to be full-scale = 1.212. To modulate this gain, the fine register is programmed using the above equation. With a full-scale ADC input, the fine register resolution is a 12LSB peak-to-peak (see Table 4 for NCOARSE = 32). Table 4 Gain correspondence (FINE) GAIN 0.825 0.878 Vi TO BE FULL-SCALE 1.212 1.139
The default programmed value is: * Programmed code = 127 * Clamp code = 0 * ADC output = 0. COARSE AND FINE REGISTERS These two registers enable the gain control, the AGC gain with the coarse register and the reference voltage with the fine register. The coarse register programming equation is as follows: N COARSE + 1 1 GAIN = --------------------------------------------- x ----- = N FINE 16 V ref 1 - ------------------ 32 x 16 N COARSE + 1 ------------------------------------------------ x 32 V ref ( 512 - N FINE ) Where: Vref = 2.5 V. The gain correspondence is given in Table 3. The gain is linear with reference to the programming code (NFINE = 0).
NFINE 0 31
The default programmed value is: NFINE = 0. CONTROL REGISTER COAST and HSYNC signals can be inverted by setting the I2C-bus control bits V level and H level respectively. When V level and H level are set to zero respectively, COAST and HSYNC are active HIGH. The bit `edge' defines the rising or falling edge of CKREF to synchronise the PLL. It will be on the rising edge if the bit is at logic 0 and on the falling edge if the bit is at logic 1. The bits Up and Do are used for the test, to force the charge pump current. These bits have to be logic 0 during normal use. The bits Ip0, Ip1 and Ip2 control the charge pump current, to increase the bandwidth of the PLL, as shown in Table 5.
1999 Mar 09
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Philips Semiconductors
Product specification
Triple high speed Analog-to-Digital Converter (ADC)
Table 5 Ip2 0 0 0 0 1 1 1 1 Charge-pump current control Ip1 0 0 1 1 0 0 1 1 Ip0 0 1 0 1 0 1 0 1 CURRENT (A) 6.25 12.5 25 50 100 200 400 700 Table 7 VCO1 1 0 1 1 VCO gain control VCO0 0 1 0 1 VCO gain (MHz/V) 60 30 60 100
TDA8752
PIXEL CLOCK FREQUENCY RANGE (MHz) 10 to 17 17 to 35 35 to 60 60 to 100
The bits VCO1 and VCO0 control the VCO gain. The default programmed value is as follows: * Internal resistance = 16 k * VCO gain = 15 MHz/V. DIVIDER REGISTER This register controls the PLL frequency. The bits are the LSB bits. The default programmed value is 0011 0010 0000 = 800. The MSB bits (Di11, Di10, Di9) and the LSB bit (Di0) have to be programmed before the bits Di8 to Di1 to have the required divider ratio. The bit Di0 is used for the parity divider number = Di0 = 0 = even number Di0 = 1 = odd number. It should be noted that if the I2C-bus programming is done in mode = 1 and the bit Di0 has to be toggled, then the registers have to be loaded twice to have the update divider ratio. POWER-DOWN MODE * When the supply is completely switched off, the registers are set to their default values; in that event they have to be reprogrammed if the required settings are different (e.g. through an EEPROM) * When the device is in power-down mode, the previously programmed register values remain unaffected. PHASEA AND PHASEB REGISTERS The bit Cka is logic 0 when the used clock is the PLL clock, and logic 1 when the used clock is the external clock. The bit Ckb is logic 0 when the second clock is not used. The bits Pa4 to Pa0 and Pb4 to Pb0 are used to program the phase shift for the clock, CKADCO, CKAO and CKBO (see Table 8).
The default programmed value is as follows: * Charge pump current = 100 A * Test bits: no test mode; bits Up and Do at logic 0 * Rising edge of CKREF: bit edge at logic 0 * COAST and HSYNC inputs are active HIGH: V level and H level at logic 0. VCO REGISTER The bits Z2, Z1 and Z0 enable the internal resistance for the VCO filter to be selected. Table 6 Z2 0 0 0 0 1 1 1 1 VCO register bits Z1 0 0 1 1 0 0 1 1 Z0 0 1 0 1 0 1 0 1 RESISTANCE (k) high impedance 128 32 16 8 4 2 1
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Philips Semiconductors
Product specification
Triple high speed Analog-to-Digital Converter (ADC)
Table 8 Phase registers bits Pa3, Pb3 0 0 1 1 Pa2, Pb2 0 0 1 1 Pa1, Pb1 0 0 1 1 Pa0, Pb0 0 1 0 1
TDA8752
Pa4, Pb4 0 0 1 1
PHASE SHIFT () 0 11.25 337.5 348.75
The default programmed value is as follows: * No external clock: CKA at logic 0 * No use of the second clock: CKB at logic 0 * Phase shift for CKAO and CKADCO = 0 * Phase shift for CKBO = 0. I2C-bus protocol Table 9 A7 1 I2C-bus address A6 0 A5 0 A4 1 A3 1 A2 ADD2 A1 ADD1 A0 0
The I2C-bus address of the circuit is 10011 xx0. Bits A2 and A1 are fixed by the potential on pins ADD1 and ADD2. Thus, four TDA8752s can be used on the same system, using the addresses for ADD1 and ADD2 with the I2C-bus. The A0 bit must always be equal to logic 0 because it is not possible to read the data in the register. The timing and protocol for the I2C-bus are standard. Two sequences are available, see Tables 10 and 11. Table 10 Address sequence for mode 0 S IC ADDRESS ACK SUBADDRESS REGISTER1 ACK DATA REGISTER1 (see Table 1) ACK SUBADDRESS REGISTER2 ACK .... P
Where: S = START condition, ACK = acknowledge and P = STOP condition. Table 11 Address sequence for mode 1 S IC ADDRESS ACK SUBADDRESS xxx1 1111 ACK DATA REGISTER1 (see Table 1) ACK DATA REGISTER2 ACK .... P
Where: S = START condition, ACK = acknowledge and P = STOP condition.
1999 Mar 09
20
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 1999 Mar 09 21 Fig.10 3-wire serial bus protocol. Product specification Philips Semiconductors 3-wire protocol
Triple high speed Analog-to-Digital Converter (ADC)
For the 3-wire serial bus the first byte refers to the register address which is programmed. The second byte refers to the data to be sent to the chosen register (see Table 1). The acquisition is achieved via SEN. Using the 3-wire interface, an indefinite number of ICs can operate on the same system. Pin SEN is used to validate the circuits.
SEN tr3W = 600 ns 1 SCL ts3W = 100 ns SDA X X X X A3 A2 A1 A0 th3W = 100 ns X D7 D6 D5 D4 D3 D2 D1 D0 X 9 1 9 100 ns
MGG365
TDA8752
Philips Semiconductors
Product specification
Triple high speed Analog-to-Digital Converter (ADC)
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VCCA VCCD VDDD VCCO VCC PARAMETER analog supply voltage digital supply voltage logic input voltage output stages supply voltage supply voltage differences VCCA - VCCD VCCO - VCCD, VCCO - VDDD VCCA - VDDD, VCCD - VDDD VCCA - VCCO Vi(RGB) Io Tstg Tamb Tj HANDLING RGB input voltage range output current storage temperature operating ambient temperature junction temperature referenced to AGND -1.0 -1.0 -1.0 -1.0 -0.3 - -55 0 - +1.0 +1.0 +1.0 +1.0 +7.0 10 CONDITIONS MIN. -0.3 -0.3 -0.3 -0.3
TDA8752
MAX. +7.0 +7.0 +7.0 +7.0 V V V V V V V V V
UNIT
mA C C C
+150 70 150
Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is desirable to take normal precautions appropriate to handling integrated circuits. THERMAL CHARACTERISTICS SYMBOL Rth(j-a) PARAMETER thermal resistance from junction to ambient CONDITIONS in free air VALUE 52 UNIT K/W
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Philips Semiconductors
Product specification
Triple high speed Analog-to-Digital Converter (ADC)
TDA8752
CHARACTERISTICS VCCA = V11 (or V19, V27 or V99) referenced to AGND (V13, V21, V29 or V96 = 4.75 to 5.25 V; VCCD = V95 referenced to DGND (V86) = 4.75 to 5.25 V; VDDD = V40 referenced to VSSD (V41) = 4.75 to 5.25 V; VCCO = V59 (or V69, V79 or V85) referenced to OGND (V48, V60, V70 or V82) = 4.75 to 5.25 V; AGND, DGND, OGND and VSSD short circuited together. Tamb = 0 to 70 C; typical values measured at VCCA = VDDD = VCCD = VCCO = 5 V and Tamb = 25 C; unless otherwise specified. SYMBOL Supplies VCCA VCCD VDDD VCCO ICCA IDDD ICCD ICCO ICCO(PLL) ICCA(PLL) VCC analog supply voltage digital supply voltage logic supply voltage output stages supply voltage analog supply current logic supply current for I2C-bus and 3-wire digital supply current output stages supply current output PLL supply current analog PLL supply current supply voltage differences VCCA - VCCD VCCO - VCCD, VCCO - VDDD VCCA - VDDD, VCCD - VDDD VCCA - VCCO Ptot Ppd total power consumption power consumption in power-down mode -3 dB; Tamb = 25 C full-scale (black-to-white) transition; input signal settling time < 1 ns; 1 to 99%; Tamb = 25 C Vref = 2.5 V; minimum coarse gain register; code = 32; (see Fig.8) maximum coarse gain register; code = 99; (see Fig.8) ramp input; fCLK = 100 MHz -0.25 -0.25 -0.25 -0.25 - - - - - - 1.0 87 +0.25 +0.25 +0.25 +0.25 - - V V V V W mW ramp input; fCLK = 100 MHz 4.75 4.75 4.75 4.75 - - - - - - 5.0 5.0 5.0 5.0 120 1.0 40 6 5 28 5.25 5.25 5.25 5.25 - - - - - - V V V V mA mA mA mA mA mA PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
R, G and B amplifiers B tset bandwidth settling time of the block ADC plus AGC 250 - - 4.5 - 6 MHz ns
GNCOARSE
coarse gain range
-
-1.67
-
dB
-
8
-
dB
1999 Mar 09
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Philips Semiconductors
Product specification
Triple high speed Analog-to-Digital Converter (ADC)
SYMBOL GFINE PARAMETER fine gain correction range CONDITIONS fine register input code = 0; (see Fig.9) fine register input code = 31; (see Fig.9) Gamp/T amplifier gain stability as a function of temperature gain current amplifier gain adjustment speed input voltage range (peak-to-peak value) input voltage rise time input voltage fall time channel-to-channel gain matching (RMS value) Vref = 2.5 V with 100 ppm/C maximum variation MIN. - - - 0 -0.5 - TYP. - -
TDA8752
MAX.
UNIT dB dB ppm/C
200
IGC tstab Vi(p-p) tr(Vi) tf(Vi) GE(rms)
- HSYNC active; capacitors - on pins 8, 16 and 24 = 22 nF corresponding to full-scale output fi = 100 MHz; square wave fi = 100 MHz; square wave maximum coarse gain; Tamb = 25 C minimum coarse gain; Tamb = 25 C 0.4 - - - -
20 25 - - - 1 2
- - 1.2 2.5 2.5 - -
A mdB/s V ns ns % %
Clamps PCLP precision black level noise on RGB channels = 10 mV (max.) (RMS value); Tamb = 25 C -1 - +1 LSB
tCOR1
clamp correction time to within 100 mV black level input 10 mV variation; clamp capacitor = 4.7 nF clamp correction time to less than 1 LSB clamp pulse width channel-to-channel clamp matching code clamp reference clamp register input code = 0 clamp register input code = 255 100 mV black level input variation; clamp capacitor = 4.7 nF
-
-
300
ns
tCOR2
-
-
10
lines
tW(CLP) CLPE Aoff
500 -1 - -
- - -63.5 64
2000 +1 - -
ns LSB LSB LSB
Phase-locked loop jPLL(rms) long term PLL jitter (RMS value) divider ratio reference clock frequency range output clock frequency range fCLK = 60 MHz; see Table 13 - fCLK = 100 MHz; see Table 13 - 100 15 12 450 360 - - - - - 4095 280 100 kHz MHz ps ps
DR fref fPLL 1999 Mar 09
24
Philips Semiconductors
Product specification
Triple high speed Analog-to-Digital Converter (ADC)
SYMBOL tCOASTmax trecap tcap step ADCs fs INL maximum sampling frequency TDA8752/6 TDA8752/8 DC integral non linearity from IC analog input to digital output; ramp input; fCLK = 100 MHz from IC analog input to digital output; ramp input; fCLK = 100 MHz from IC analog input to digital output; 10 kHz sine wave input; ramp input; fCLK = 100 MHz; note 1 maximum gain; fCLK = 100 MHz minimum gain; fCLK = 100 MHz Spurious free dynamic range SFDR spurious free dynamic range maximum gain; fCLK = 100 MHz minimum gain; fCLK = 100 MHz Clock timing output (CKADCO, CKBO and CKAO) ext fCLK(max) ADC clock duty cycle maximum clock frequency 100 MHz output 45 100 50 - - - - 14.7 t CLK --------2 0.1 55 - - - - - - 60 60 - - 60 100 - - - 0.5 - - PARAMETER maximum coast mode time PLL recapture time PLL capture time phase shift step CONDITIONS MIN. - when coast mode is aborted - in start-up conditions Tamb = 25 C - - - 3 - 11.25 TYP. - 5 -
TDA8752
MAX. 40
UNIT lines lines ms deg
MHz MHz LSB
1.5
DNL
DC differential non linearity
-
0.5
1.0
LSB
ENOB
effective number of bits
-
7.4
-
bits
Signal-to-noise ratio S/N signal-to-noise ratio - - 45 44 - - dB dB
dB dB
% MHz
Clock timing input (CKEXT) fCLK(max) tCPH tCPL td(CLKO) maximum clock frequency clock pulse width HIGH clock pulse width LOW delay from CKEXT to CKADCO INV set to LOW INV set to HIGH 100 3.6 4.5 13.6 - MHz ns ns ns ns
15.2 - 0.3
tsample
time difference between samples
operating in the same supply - and temperature condition
ns
1999 Mar 09
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Philips Semiconductors
Product specification
Triple high speed Analog-to-Digital Converter (ADC)
SYMBOL PARAMETER CONDITIONS MIN. TYP.
TDA8752
MAX.
UNIT
Data timing (see Fig.11); fCLK = 100 MHz; CL = 10 pF; note 2 td(s) td(o) th(o) sampling delay time output delay time output hold time referenced to CKADCO - - 4.6 - - - - - 2.4 - - - 2.4 - - - 2.0 VIL = 0.4 V VIH = 2.7 V 400 - - - - - - - -3.3 5.5 - -2.6 - - - - - ns ns ns
3-state output delay time; (see Fig.12) tdZH tdZL tdHZ tdLZ output enable HIGH output enable LOW output disable HIGH output disable LOW 12 10 50 65 ns ns ns ns
PLL clock output VOL VOH IOL IOH LOW-level output voltage HIGH-level output voltage LOW-level output current HIGH-level output current Io = 1 mA Io = - 1 mA VOL = 0.4 V VOH = 2.7 V 0.3 3.5 2 -0.4 0.8 - - - V V mA mA
ADC data outputs VOL VOH IOL IOH LOW-level output voltage HIGH-level output voltage LOW-level output current HIGH-level output current Io = 1 mA Io = - 1 mA VOL = 0.4 V VOH = 2.7 V 0 VCCD 2 -0.5 - - - - 4 4.5 0.8 - - - V V mA mA
TTL digital inputs (CKREF, COAST, CKEXT, INV, HSYNC and CLP) VIL VIH IIL IIH Zi Ci LOW level input voltage HIGH level input voltage LOW level input current HIGH level input current input impedance input capacitance 0.8 - - 100 - - - - - V V A A k pF
3-wire serial bus treset tsu th reset time of the chip before 3-wire communication data set-up time data hold time 600 100 100 ns ns ns
I2C-bus; see note 3 fSCL tBUF clock frequency time the bus must be free before new transmission can start 0 4.7 - - 100 - kHz s
1999 Mar 09
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Philips Semiconductors
Product specification
Triple high speed Analog-to-Digital Converter (ADC)
SYMBOL tHD;STA tSU;STA tCKL tCKH tSU;DAT tHD;DAT tr tf tSU;STOP CL(bus) PARAMETER start condition hold time start condition set-up time LOW level clock period HIGH level clock period data set-up time data hold time SDA and SCL rise time SDA and SCL fall time stop condition set-up time capacitive load for each bus line for fSCL = 100 kHz for fSCL = 100 kHz repeated start CONDITIONS MIN. 4.0 4.7 4.7 4.0 250 0 - - 4.0 - - - - - - - - - - - TYP. - - - - - -
TDA8752
MAX.
UNIT s s s s ns ns s ns s pF
1.0 300 - 400
Notes to the characteristics 1. Effective bits are obtained via a Fast Fourier Transform (FFT) treatment taking 8000 acquisition points per equivalent fundamental period. The calculation takes into account all harmonics and noise up to half clock frequency (NYQUIST frequency). Conversion-to-noise ratio: S/N = EB x 6.02 + 1.76 dB. 2. Output data acquisition is available after the maximum delay time td(o), which is the time during which the data is available. All the timings are given for a 10 pF capacitive load. A higher load can be used but the timing must then be rechecked. 3. The I2C-bus timings are given for a frequency of 100 kbit/s (100 kHz). This bus can be used at a frequency of 400 kbit/s (400 kHz).
handbook, full pagewidth
tCPH n CKADCO
tCPL 50 % = 1.4 V
td(o) DATA R0 to R7, ROR G0 to G7, GOR B0 to B7, BOR 2.4 V In - 1 In In + 1 th(o) td(s) VlN sample N + 1 sample N sample N + 2 In + 2 1.4 V 0.4 V
MGL103
Fig.11 Timing diagram.
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Philips Semiconductors
Product specification
Triple high speed Analog-to-Digital Converter (ADC)
TDA8752
V handbook, full pagewidthCCD OE 50%
tdHZ HIGH 90% output data tdLZ HIGH output data LOW 10% tdZL LOW
tdZH
50%
VCCD 50% 3.3 k TDA8752 10 pF OE
MGD695
S1
tOE = 100 kHz.
Fig.12 Timing diagram and test conditions of 3-state output delay time.
Table 12 Test conditions for Fig.12 TEST tdLZ tdZl tdHZ tdZH SWITCH S1 VCCD VCCD GND GND
1999 Mar 09
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This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 1999 Mar 09 29 Product specification APPLICATION INFORMATION Philips Semiconductors Table 13 Examples of PLL settings and performances; note 1 VIDEO STANDARDS CGA: 640 x 200 VGA: 640 x 480 VESA: 800 x 600 VESA: 1024 x 768 SUN: 1152 x 900 Notes 1. Values measured at VCCA = VDDD = VCCD = VCCO = 5 V and Tamb = 25C. 2. PLL long-term time jitter is measured at the end of the video line, where it is at its maximum. 3. Measured between 0 and 70 C. fref (kHz) 15.75 31.5 48.08 60.02 66.67 fCLK (MHz) 14.3 25.2 50 78.8 100 N 912 800 1040 1312 1500 KO (MHz/V) 15 30 60 100 100 CZ (nF) 150 150 150 150 150 CP (nF) 1 1 1 1 1 IP (A) 200 400 700 700 700 Z (k) 4 2 1 1 1 LONG TIME JITTER(2) ps (RMS) - 610 480 380 360 ns (p-p) - 3.6 2.9 2.3 2.2 PLL PHASE DRIFT(3) (ns) 1.2 0.7 0.55 0.3 0.3
Triple high speed Analog-to-Digital Converter (ADC) TDA8752
Philips Semiconductors
Product specification
Triple high speed Analog-to-Digital Converter (ADC)
TDA8752
handbook, full pagewidth
33 nF CZ VCCA(PLL) n.c. n.c. 10 nF
PWDWN CKBO 150 pF COAST CKADCO OE CLP CP VCCO(PLL) CKEXT AGNDPLL OGNDPLL HSYNC CKREF DGND VCCD CKAO INV CKREFO VCCOR R7 R6 R5 R4 R3 R2 R1 R0 OGNDR VCCOG G7 G6 G5 G4 G3 G2 G1 G0 OGNDG VCCOB B7 B6 B5 B4 B3 B2 B1 n.c.
1
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80
2.5 V
RIN
GIN
BIN
DEC2 2 79 Vref 3 78 1.5 nF DEC1 4 77 n.c. 5 76 RAGC 6 75 10 nF RBOT 7 74 22 nF RGAINC 8 73 4.7 nF RCLP 9 72 10 nF RDEC 10 71 VCCAR 11 70 100 nF RIN 12 69 AGNDR 13 68 75 or 50 GAGC 14 67 10 nF GBOT 15 66 22 nF GGAINC TDA8752 16 65 4.7 nF GCLP 17 64 10 nF GDEC 18 63 VCCAG 19 62 100 nF GIN 20 61 AGNDG 21 60 75 or 50 BAGC 22 59 10 nF BBOT 23 58 22 nF BGAINC 24 57 4.7 nF BCLP 25 56 10 nF BCDEC 26 55 VCCAB 27 54 100 nF BIN 28 53 AGNDB 29 52 75 or 50 n.c. 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 n.c. ADD1 TCK DIS I2C/3W ADD2 TDO SEN VDDD VSSD n.c. ROR BOR n.c. GOR B0 n.c. OGNDB
4.7 4.7 k k SDA SCL VDDD VDDD
MGG371
All supply pins have to be decoupled, with two capacitors: one for high frequencies (approximately 1 nF) and one for the low frequencies (approximately 100 nF or higher).
Fig.13 Application diagram.
1999 Mar 09
30
Philips Semiconductors
Product specification
Triple high speed Analog-to-Digital Converter (ADC)
PACKAGE OUTLINE QFP100: plastic quad flat package; 100 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mm
TDA8752
SOT317-2
c
y X
80 81
51 50 ZE
A
e E HE A A2 A1 (A 3) Lp bp 100 1 wM D HD ZD B vM B 30 vMA 31 detail X L
wM pin 1 index
e
bp
0
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 3.20 A1 0.25 0.05 A2 2.90 2.65 A3 0.25 bp 0.40 0.25 c 0.25 0.14 D (1) 20.1 19.9 E (1) 14.1 13.9 e 0.65 HD 24.2 23.6 HE 18.2 17.6 L 1.95 Lp 1.0 0.6 v 0.2 w 0.15 y 0.1 Z D (1) Z E(1) 0.8 0.4 1.0 0.6 7 0o
o
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT317-2 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION
ISSUE DATE 95-02-04 97-08-01
1999 Mar 09
31
Philips Semiconductors
Product specification
Triple high speed Analog-to-Digital Converter (ADC)
SOLDERING Introduction to soldering surface mount packages This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering is not always suitable for surface mount ICs, or for printed-circuit boards with high population densities. In these situations reflow soldering is often used. Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 C. The top-surface temperature of the packages should preferable be kept below 230 C. Wave soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results:
TDA8752
* Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. * For packages with leads on two sides and a pitch (e): - larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. * For packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Manual soldering Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
1999 Mar 09
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Philips Semiconductors
Product specification
Triple high speed Analog-to-Digital Converter (ADC)
Suitability of surface mount IC packages for wave and reflow soldering methods SOLDERING METHOD PACKAGE WAVE BGA, SQFP PLCC(3), SO, SOJ not suitable suitable(2) suitable not recommended(3)(4) not recommended(5) suitable suitable suitable suitable suitable HLQFP, HSQFP, HSOP, HTSSOP, SMS not LQFP, QFP, TQFP SSOP, TSSOP, VSO Notes
TDA8752
REFLOW(1)
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the "Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods". 2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
1999 Mar 09
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Philips Semiconductors
Product specification
Triple high speed Analog-to-Digital Converter (ADC)
DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
TDA8752
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011.
1999 Mar 09
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Philips Semiconductors
Product specification
Triple high speed Analog-to-Digital Converter (ADC)
NOTES
TDA8752
1999 Mar 09
35
Philips Semiconductors - a worldwide company
Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 9805 4455, Fax. +61 2 9805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. +43 1 60 101 1248, Fax. +43 1 60 101 1210 Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6, 220050 MINSK, Tel. +375 172 20 0733, Fax. +375 172 20 0773 Belgium: see The Netherlands Brazil: see South America Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor, 51 James Bourchier Blvd., 1407 SOFIA, Tel. +359 2 68 9211, Fax. +359 2 68 9102 Canada: PHILIPS SEMICONDUCTORS/COMPONENTS, Tel. +1 800 234 7381, Fax. +1 800 943 0087 China/Hong Kong: 501 Hong Kong Industrial Technology Centre, 72 Tat Chee Avenue, Kowloon Tong, HONG KONG, Tel. +852 2319 7888, Fax. +852 2319 7700 Colombia: see South America Czech Republic: see Austria Denmark: Sydhavnsgade 23, 1780 COPENHAGEN V, Tel. +45 33 29 3333, Fax. +45 33 29 3905 Finland: Sinikalliontie 3, FIN-02630 ESPOO, Tel. +358 9 615 800, Fax. +358 9 6158 0920 France: 51 Rue Carnot, BP317, 92156 SURESNES Cedex, Tel. +33 1 4099 6161, Fax. +33 1 4099 6427 Germany: Hammerbrookstrae 69, D-20097 HAMBURG, Tel. +49 40 2353 60, Fax. +49 40 2353 6300 Greece: No. 15, 25th March Street, GR 17778 TAVROS/ATHENS, Tel. +30 1 489 4339/4239, Fax. +30 1 481 4240 Hungary: see Austria India: Philips INDIA Ltd, Band Box Building, 2nd floor, 254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025, Tel. +91 22 493 8541, Fax. +91 22 493 0966 Indonesia: PT Philips Development Corporation, Semiconductors Division, Gedung Philips, Jl. Buncit Raya Kav.99-100, JAKARTA 12510, Tel. +62 21 794 0040 ext. 2501, Fax. +62 21 794 0080 Ireland: Newstead, Clonskeagh, DUBLIN 14, Tel. +353 1 7640 000, Fax. +353 1 7640 200 Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053, TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007 Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3, 20124 MILANO, Tel. +39 2 6752 2531, Fax. +39 2 6752 2557 Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108-8507, Tel. +81 3 3740 5130, Fax. +81 3 3740 5077 Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL, Tel. +82 2 709 1412, Fax. +82 2 709 1415 Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR, Tel. +60 3 750 5214, Fax. +60 3 757 4880 Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905, Tel. +9-5 800 234 7381, Fax +9-5 800 943 0087 Middle East: see Italy Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB, Tel. +31 40 27 82785, Fax. +31 40 27 88399 New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND, Tel. +64 9 849 4160, Fax. +64 9 849 7811 Norway: Box 1, Manglerud 0612, OSLO, Tel. +47 22 74 8000, Fax. +47 22 74 8341 Pakistan: see Singapore Philippines: Philips Semiconductors Philippines Inc., 106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI, Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474 Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA, Tel. +48 22 612 2831, Fax. +48 22 612 2327 Portugal: see Spain Romania: see Italy Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW, Tel. +7 095 755 6918, Fax. +7 095 755 6919 Singapore: Lorong 1, Toa Payoh, SINGAPORE 319762, Tel. +65 350 2538, Fax. +65 251 6500 Slovakia: see Austria Slovenia: see Italy South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale, 2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000, Tel. +27 11 470 5911, Fax. +27 11 470 5494 South America: Al. Vicente Pinzon, 173, 6th floor, 04547-130 SAO PAULO, SP, Brazil, Tel. +55 11 821 2333, Fax. +55 11 821 2382 Spain: Balmes 22, 08007 BARCELONA, Tel. +34 93 301 6312, Fax. +34 93 301 4107 Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM, Tel. +46 8 5985 2000, Fax. +46 8 5985 2745 Switzerland: Allmendstrasse 140, CH-8027 ZURICH, Tel. +41 1 488 2741 Fax. +41 1 488 3263 Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1, TAIPEI, Taiwan Tel. +886 2 2134 2886, Fax. +886 2 2134 2874 Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd., 209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260, Tel. +66 2 745 4090, Fax. +66 2 398 0793 Turkey: Talatpasa Cad. No. 5, 80640 GULTEPE/ISTANBUL, Tel. +90 212 279 2770, Fax. +90 212 282 6707 Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7, 252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461 United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381, Fax. +1 800 943 0087 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. +381 11 62 5344, Fax.+381 11 63 5777 Internet: http://www.semiconductors.philips.com
For all other countries apply to: Philips Semiconductors, International Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 1999
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All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
545004/750/05/pp36
Date of release: 1999 Mar 09
Document order number:
9397 750 05306

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